As is known, a central processing unit (CPU) is electrically connected to a control chip, which is generally a bridge chip, via a front side bus. When the CPU issue a request, e.g. an access request to a memory and/or a read/write request to an I/O device, the control chip will perform the corresponding access or read/write operation according to the request from the CPU.
In general, the CPU is designed with a pipeline for permitting multi-requests at the same time. Complying with the pipeline design of the CPU, the control chip is supposed to be able to deal with the consecutive outstanding requests from the CPU. Therefore, a-queue is built in the control chip for storing the pending requests from the CPU before the requests are processed individually.
The capacities of the CPU and the control chip for processing requests, however, are limited to some extent. When the capacity or the allowed outstanding request number of the control chip is smaller than that of the CPU, the control chip has to timely inform the CPU of the approaching threshold and block any further request from the CPU. In prior art, The CPU is provided therewith a block-next-request (BNR) signal line. In response to a block-next-request signal transmitted on the line, the request from and/or to the CPU is blocked.
Please refer to FIG. 1 that illustrates the relationship between a BNR signal between the CPU and the control chip and an address strobe signal (ADS) generated by the bus owner, i.e. either the CPU or the control chip. When it is the CPU that dominates the bus, the ADS will be pulled “low” for one cycle in order to inform the control chip of the coming request. For example, as shown in FIG. 1, the low level of the ADS at Cycle 2 indicates that the CPU outputs a request. Meanwhile, if the request number stored in the queue of the control chip is determined to approach the limit, the BNR signal is asserted “low” by the control chip at Cycle 2 to suspend next request from the CPU. The CPU first samples the low level of the BNR signal at Cycle 2, and then the last request from the CPU is outputted at Cycle 4 and the request from the CPU is suspended from Cycle 5. The CPU samples the BNR signal at alternate cycles after the suspension, and is allowed to output requests again when detecting a high level of the BNR signal. For example, as shown, the BNR signal is detected to be of a low level at Cycle 4 and Cycle 6. It means that the control chip has no capacity for receiving any further request. Afterwards, at Cycle 8, the BNR signal is detected to be of a high level, so next request from the CPU is allowable to be issued to the control chip. The CPU then outputs a new request to the control chip at Cycle 10. A similar situation occurs in the following cycles. Cycle 18 is the last one when the CPU is allowed to output requests because of the low level of the BNR signal at Cycle 16 to block requests. The CPU is blocked to output any request via the front side bus from Cycle 19 to Cycle 21. Then, the request at Cycle 22 is permissible again due to the high-level of the BNR signal at Cycle 20.
In the prior art, a drive circuit is additionally provided in the control chip for pulling the BNR signal low when necessary so as to block the request from the CPU. The BNR signal occupies one pin of the control chip, and the BNR signal drive circuit also occupies certain area of the control chip. In addition, the BNR signal drive circuit consumes power, which is disadvantageous for electric apparatus.